@@ -140,1 +139,4 @@
  * implementation of pico_get_unique_id() for an example of this.
+ * 
+ * \if rp2040_specific
+ * On RP2040 the chip select index is ignored, as there is only one chip select.

@@ -140,1 +139,4 @@
  * implementation of pico_get_unique_id() for an example of this.
+ * 
+ * \if rp2040_specific
+ * On RP2040 the chip select index is ignored, as there is only one chip select.

@@ -140,1 +139,4 @@
  * implementation of pico_get_unique_id() for an example of this.
+ * 
+ * \if rp2040_specific
+ * On RP2040 the chip select index is ignored, as there is only one chip select.

@@ -140,1 +139,4 @@
  * implementation of pico_get_unique_id() for an example of this.
+ * 
+ * \if rp2040_specific
+ * On RP2040 the chip select index is ignored, as there is only one chip select.

@@ -0,0 +1,269 @@
+/*

@@ -0,0 +1,269 @@
+/*

@@ -0,0 +1,269 @@
+/*

@@ -0,0 +1,269 @@
+/*

@@ -0,0 +1,269 @@
+/*

@@ -0,0 +1,269 @@
+/*

@@ -0,0 +1,269 @@
+/*

@@ -0,0 +1,269 @@
+/*

@@ -0,0 +1,269 @@
+/*

@@ -0,0 +1,269 @@
+/*

@@ -0,0 +241,4 @@
+/*! \brief Provide a static PSRAM allocation, or malloc if PSRAM is not available
+ *  \ingroup hardware_psram
+ *
+ * This will allocate a static buffer in PSRAM and if available use that, otherwise it will use the heap.

@@ -0,0 +1,269 @@
+/*

@@ -0,0 +1,269 @@
+/*

@@ -140,1 +139,4 @@
  * implementation of pico_get_unique_id() for an example of this.
+ * 
+ * \if rp2040_specific
+ * On RP2040 the chip select index is ignored, as there is only one chip select.

@@ -0,0 +1,269 @@
+/*

@@ -261,15 +274,16 @@ static void __no_inline_not_in_flash_func(flash_cs_force)(bool high) {
         IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS
     );

@@ -0,0 +1,269 @@
+/*

@@ -0,0 +1,269 @@
+/*

@@ -0,0 +157,4 @@
+/*! \brief Detect PSRAM size
+ *  \ingroup hardware_psram
+ *
+ * This will read the ID of the PSRAM chip and return the size based on the ID.

@@ -104,0 +106,4 @@
+    #
+    # \param\ TARGET The target to override the FLASH size for
+    # \param\ FLASH_SIZE The FLASH size to set for the target
+    function(pico_override_flash_size TARGET FLASH_SIZE)

@@ -104,0 +106,4 @@
+    #
+    # \param\ TARGET The target to override the FLASH size for
+    # \param\ FLASH_SIZE The FLASH size to set for the target
+    function(pico_override_flash_size TARGET FLASH_SIZE)

@@ -104,0 +106,4 @@
+    #
+    # \param\ TARGET The target to override the FLASH size for
+    # \param\ FLASH_SIZE The FLASH size to set for the target
+    function(pico_override_flash_size TARGET FLASH_SIZE)

@@ -104,0 +106,4 @@
+    #
+    # \param\ TARGET The target to override the FLASH size for
+    # \param\ FLASH_SIZE The FLASH size to set for the target
+    function(pico_override_flash_size TARGET FLASH_SIZE)

@@ -104,0 +106,4 @@
+    #
+    # \param\ TARGET The target to override the FLASH size for
+    # \param\ FLASH_SIZE The FLASH size to set for the target
+    function(pico_override_flash_size TARGET FLASH_SIZE)

@@ -261,15 +274,16 @@ static void __no_inline_not_in_flash_func(flash_cs_force)(bool high) {
         IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS
     );

@@ -0,0 +1,269 @@
+/*

@@ -0,0 +1,269 @@
+/*

@@ -0,0 +157,4 @@
+/*! \brief Detect PSRAM size
+ *  \ingroup hardware_psram
+ *
+ * This will read the ID of the PSRAM chip and return the size based on the ID.

@@ -138,16 +137,44 @@ void flash_get_unique_id(uint8_t *id_out);
  * it is recommended that this function only be used to extract flash metadata

@@ -0,0 +1,269 @@
+/*

@@ -0,0 +171,4 @@
+ *  \ingroup hardware_psram
+ *
+ * This runs \ref psram_detect_size() for each CS GPIO in the array in turn,
+ * and returns the size as soon as a PSRAM chip is detected.

@@ -0,0 +1,449 @@
+/*

@@ -0,0 +171,4 @@
+ *  \ingroup hardware_psram
+ *
+ * This runs \ref psram_detect_size() for each CS GPIO in the array in turn,
+ * and returns the size as soon as a PSRAM chip is detected.

@@ -0,0 +28,4 @@
+    // Currently supports APS6404 and ISSI PSRAM
+    size_t psram_size = 0;
+
+    if (kgd == PICO_DEFAULT_PSRAM_ID) { // Known Good Die - expects 0x5D

@@ -0,0 +28,4 @@
+    // Currently supports APS6404 and ISSI PSRAM
+    size_t psram_size = 0;
+
+    if (kgd == PICO_DEFAULT_PSRAM_ID) { // Known Good Die - expects 0x5D

@@ -0,0 +1,449 @@
+/*

@@ -0,0 +1,449 @@
+/*

@@ -0,0 +1,269 @@
+/*

@@ -0,0 +1,269 @@
+/*

@@ -0,0 +1,449 @@
+/*

@@ -0,0 +1,449 @@
+/*

@@ -0,0 +1,269 @@
+/*

@@ -0,0 +1,449 @@
+/*

@@ -0,0 +1,449 @@
+/*

@@ -0,0 +171,4 @@
+ *  \ingroup hardware_psram
+ *
+ * This runs \ref psram_detect_size() for each CS GPIO in the array in turn,
+ * and returns the size as soon as a PSRAM chip is detected.

@@ -0,0 +173,4 @@
+ * This runs \ref psram_detect_size() for each CS GPIO in the array in turn,
+ * and returns the size as soon as a PSRAM chip is detected.
+ *
+ * This will setup the CS GPIO using flash_devinfo if PSRAM is found.

@@ -0,0 +179,4 @@
+ * \param num Number of CS GPIOs in the array
+ * \return size of PSRAM, or 0 if none found
+ */
+size_t psram_detect_cs_and_size(uint8_t *cs_gpios, size_t num);

@@ -0,0 +82,4 @@
+        gpio_set_function(gpio, GPIO_FUNC_XIP_CS1);
+        psram_size = psram_detect_size();
+        if (psram_size > 0) {
+            // CS GPIO found, so will be left configured in flash_devinfo

@@ -0,0 +1,449 @@
+/*

@@ -0,0 +1,449 @@
+/*

@@ -0,0 +179,4 @@
+ * \param num Number of CS GPIOs in the array
+ * \return size of PSRAM, or 0 if none found
+ */
+size_t psram_detect_cs_and_size(uint8_t *cs_gpios, size_t num);

@@ -0,0 +82,4 @@
+        gpio_set_function(gpio, GPIO_FUNC_XIP_CS1);
+        psram_size = psram_detect_size();
+        if (psram_size > 0) {
+            // CS GPIO found, so will be left configured in flash_devinfo

@@ -0,0 +320,4 @@
+}
+
+bool psram_check_address(void* addr) {
+    uint32_t offset = (uint32_t)addr - (XIP_BASE + flash_devinfo_size_to_bytes(FLASH_DEVINFO_SIZE_MAX));

@@ -0,0 +1,449 @@
+/*

@@ -0,0 +346,4 @@
+    bool __unused flash_devinfo_not_configured = flash_devinfo_get_cs_size(1) == FLASH_DEVINFO_SIZE_NONE;
+
+    // Setup flash_devinfo from compile definitions
+    #if defined(PICO_PSRAM_CS_PIN) && !PICO_AUTO_DETECT_PSRAM_CS

@@ -0,0 +1,449 @@
+/*

@@ -0,0 +1,449 @@
+/*

@@ -0,0 +320,4 @@
+}
+
+bool psram_check_address(void* addr) {
+    uint32_t offset = (uint32_t)addr - (XIP_BASE + flash_devinfo_size_to_bytes(FLASH_DEVINFO_SIZE_MAX));

@@ -0,0 +1,449 @@
+/*

@@ -0,0 +346,4 @@
+    bool __unused flash_devinfo_not_configured = flash_devinfo_get_cs_size(1) == FLASH_DEVINFO_SIZE_NONE;
+
+    // Setup flash_devinfo from compile definitions
+    #if defined(PICO_PSRAM_CS_PIN) && !PICO_AUTO_DETECT_PSRAM_CS

@@ -0,0 +1,449 @@
+/*

@@ -0,0 +1,269 @@
+/*

@@ -0,0 +1,269 @@
+/*

@@ -0,0 +320,4 @@
+}
+
+bool psram_check_address(void* addr) {
+    uint32_t offset = (uint32_t)addr - (XIP_BASE + flash_devinfo_size_to_bytes(FLASH_DEVINFO_SIZE_MAX));

@@ -0,0 +1,449 @@
+/*

@@ -0,0 +346,4 @@
+    bool __unused flash_devinfo_not_configured = flash_devinfo_get_cs_size(1) == FLASH_DEVINFO_SIZE_NONE;
+
+    // Setup flash_devinfo from compile definitions
+    #if defined(PICO_PSRAM_CS_PIN) && !PICO_AUTO_DETECT_PSRAM_CS

@@ -0,0 +1,269 @@
+/*

@@ -0,0 +1,449 @@
+/*

@@ -0,0 +1,269 @@
+/*

@@ -0,0 +1,449 @@
+/*

@@ -0,0 +346,4 @@
+    bool __unused flash_devinfo_not_configured = flash_devinfo_get_cs_size(1) == FLASH_DEVINFO_SIZE_NONE;
+
+    // Setup flash_devinfo from compile definitions
+    #if defined(PICO_PSRAM_CS_PIN) && !PICO_AUTO_DETECT_PSRAM_CS

@@ -0,0 +1,449 @@
+/*

@@ -0,0 +392,4 @@
+    uint32_t psram_words = (uint32_t)(&__psram_end__ - &__psram_start__);
+    if (psram_words > psram_word_size) {
+        // Setup to bus fault for variables that don't fit in available PSRAM
+        int clear_regions = 0; // Clear no regions by default

@@ -0,0 +1,269 @@
+/*

@@ -0,0 +1,269 @@
+/*

@@ -0,0 +23,4 @@
+ *   2. If `PICO_AUTO_DETECT_PSRAM` is set it will attempt to detect PSRAM size and CS GPIO
+ *      on CS1. This will attempt to use all available QMI CS1n GPIOs as chip selects, so they
+ *      will be wiggled. By default, it will skip over some which are defined in the board
+ *      header (see `PICO_AUTO_DETECT_PSRAM_CS_SKIP_DEFAULTS`).

@@ -0,0 +1,269 @@
+/*

@@ -0,0 +1,269 @@
+/*

@@ -0,0 +41,4 @@
+ * If there are variables placed in PSRAM, XIP will be set up to cause bus faults on any
+ * access to PSRAM addresses greater than the size available. The \ref psram_check_address
+ * function should be used before accessing variables in PSRAM when auto-detection is on,
+ * to prevent these bus faults.

@@ -0,0 +1,269 @@
+/*

@@ -0,0 +1,269 @@
+/*

@@ -0,0 +41,4 @@
+ * If there are variables placed in PSRAM, XIP will be set up to cause bus faults on any
+ * access to PSRAM addresses greater than the size available. The \ref psram_check_address
+ * function should be used before accessing variables in PSRAM when auto-detection is on,
+ * to prevent these bus faults.

@@ -0,0 +1,269 @@
+/*

@@ -0,0 +1,269 @@
+/*

@@ -0,0 +23,4 @@
+ *   2. If `PICO_AUTO_DETECT_PSRAM` is set it will attempt to detect PSRAM size and CS GPIO
+ *      on CS1. This will attempt to use all available QMI CS1n GPIOs as chip selects, so they
+ *      will be wiggled. By default, it will skip over some which are defined in the board
+ *      header (see `PICO_AUTO_DETECT_PSRAM_CS_SKIP_DEFAULTS`).

@@ -0,0 +94,4 @@
+    }
+
+    return psram_size;
+}

@@ -0,0 +205,4 @@
+    }
+    uint32_t rxdelay = divisor;
+    if (clock_hz / divisor > 100000000) {
+        rxdelay += 1;

@@ -0,0 +205,4 @@
+    }
+    uint32_t rxdelay = divisor;
+    if (clock_hz / divisor > 100000000) {
+        rxdelay += 1;

@@ -0,0 +94,4 @@
+    }
+
+    return psram_size;
+}

@@ -0,0 +94,4 @@
+    }
+
+    return psram_size;
+}

@@ -0,0 +94,4 @@
+    }
+
+    return psram_size;
+}

@@ -0,0 +1,449 @@
+/*

@@ -0,0 +94,4 @@
+    }
+
+    return psram_size;
+}