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mh_sha1: add an mh_sha1 assembly implementation with vector extension for riscv64 #168

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HeliC829 wants to merge 1 commit from HeliC829/risc-v-mh-sha1 into master
pull from: HeliC829/risc-v-mh-sha1
merge into: gh-intel:master
Conversation 11 Commits 1 Files changed 5 +562 -1
HeliC829 commented 2025-12-21 02:36:00 -06:00 (Migrated from github.com)

This PR added an mh_sha1 assembly implementation with vector extension for riscv64.

Origin C implementation:

mh_sha1_update_base_warm: runtime =     247264 usecs, bandwidth 31 MB in 0.2473 sec = 132.52 MB/s
isal_mh_sha1_update_warm: runtime =    2464763 usecs, bandwidth 312 MB in 2.4648 sec = 132.95 MB/s

Assembly implementation with vector extension :

mh_sha1_update_base_warm: runtime =     213991 usecs, bandwidth 31 MB in 0.2140 sec = 153.13 MB/s
isal_mh_sha1_update_warm: runtime =     863086 usecs, bandwidth 312 MB in 0.8631 sec = 379.66 MB/s
This PR added an mh_sha1 assembly implementation with vector extension for riscv64. Origin C implementation: ``` mh_sha1_update_base_warm: runtime = 247264 usecs, bandwidth 31 MB in 0.2473 sec = 132.52 MB/s isal_mh_sha1_update_warm: runtime = 2464763 usecs, bandwidth 312 MB in 2.4648 sec = 132.95 MB/s ``` Assembly implementation with vector extension : ``` mh_sha1_update_base_warm: runtime = 213991 usecs, bandwidth 31 MB in 0.2140 sec = 153.13 MB/s isal_mh_sha1_update_warm: runtime = 863086 usecs, bandwidth 312 MB in 0.8631 sec = 379.66 MB/s ```
pablodelara commented 2025-12-30 03:20:38 -06:00 (Migrated from github.com)

This will be merged after the new release is out next month, thanks

This will be merged after the new release is out next month, thanks
HeliC829 commented 2026-08-31 03:15:15 -05:00 (Migrated from github.com)

kindly ping for merge.

kindly ping for merge.
pablodelara commented 2026-08-31 04:22:15 -05:00 (Migrated from github.com)

Sorry @HeliC829 for keeping you waiting. @sunyuechi could you review this PR? Thanks!

Sorry @HeliC829 for keeping you waiting. @sunyuechi could you review this PR? Thanks!
sunyuechi (Migrated from github.com) reviewed 2026-08-31 05:00:21 -05:00
mh_sha1/riscv64/mh_sha1_block_rvv.S
@ -0,0 +1,416 @@
/**********************************************************************
sunyuechi (Migrated from github.com) commented 2026-08-31 05:00:21 -05:00

TMP2 unused

TMP2 unused
sunyuechi (Migrated from github.com) reviewed 2026-08-31 05:00:46 -05:00
mh_sha1/riscv64/mh_sha1_block_rvv.S
@ -0,0 +1,416 @@
/**********************************************************************
sunyuechi (Migrated from github.com) commented 2026-08-31 05:00:47 -05:00

vadd.vx

vadd.vx
sunyuechi (Migrated from github.com) reviewed 2026-08-31 05:20:49 -05:00
HeliC829 (Migrated from github.com) reviewed 2026-09-02 07:32:17 -05:00
mh_sha1/riscv64/mh_sha1_block_rvv.S
@ -0,0 +1,416 @@
/**********************************************************************
HeliC829 (Migrated from github.com) commented 2026-09-02 07:32:17 -05:00

removed.

removed.
HeliC829 (Migrated from github.com) reviewed 2026-09-02 07:32:26 -05:00
mh_sha1/riscv64/mh_sha1_block_rvv.S
@ -0,0 +1,416 @@
/**********************************************************************
HeliC829 (Migrated from github.com) commented 2026-09-02 07:32:26 -05:00

done.

done.
HeliC829 (Migrated from github.com) reviewed 2026-09-02 07:33:52 -05:00
HeliC829 (Migrated from github.com) reviewed 2026-09-02 07:33:59 -05:00
sunyuechi commented 2026-09-02 10:50:23 -05:00 (Migrated from github.com)

0001-mh_sha1-process-all-16-segments-per-pass-in-the-risc.patch

The loop runs many times but vl=4 instead of something big， looks like
fixed-width SIMD usage.

You could use vl=16 and pick m1/m2/m4 based on vlen to cut the iteration
count. I tried it and got another 2-3x.

Maybe amend on top of this patch and see if anything else is worth changing，
If vl=4 is really needed, a comment would help.

[0001-mh_sha1-process-all-16-segments-per-pass-in-the-risc.patch](https://github.com/user-attachments/files/31745435/0001-mh_sha1-process-all-16-segments-per-pass-in-the-risc.patch) The loop runs many times but vl=4 instead of something big， looks like fixed-width SIMD usage. You could use vl=16 and pick m1/m2/m4 based on vlen to cut the iteration count. I tried it and got another 2-3x. Maybe amend on top of this patch and see if anything else is worth changing， If vl=4 is really needed, a comment would help.
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git switch 'master'
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