WIP: mh_sha1_murmur3_x64_128: add assembly implementation with vector extension for riscv64 #172

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HeliC829 wants to merge 2 commits from HeliC829/risc-v-mh-sha1-murmur3 into master
HeliC829 commented 2026-01-25 01:12:17 -06:00 (Migrated from github.com)

Depends on #168
This PR added an mh_sha1_murmur3_x64_128 assembly implementation with vector extension for riscv64.

Origin C implementation:

isal_mh_sha1_murmur3_x64_128_update_warm: runtime =    2676771 usecs, bandwidth 312 MB in 2.6768 sec = 122.42 MB/s

Assembly implementation with vector extension :

isal_mh_sha1_murmur3_x64_128_update_warm: runtime =     873527 usecs, bandwidth 312 MB in 0.8735 sec = 375.12 MB/s
Depends on #168 This PR added an mh_sha1_murmur3_x64_128 assembly implementation with vector extension for riscv64. Origin C implementation: ``` isal_mh_sha1_murmur3_x64_128_update_warm: runtime = 2676771 usecs, bandwidth 312 MB in 2.6768 sec = 122.42 MB/s ``` Assembly implementation with vector extension : ``` isal_mh_sha1_murmur3_x64_128_update_warm: runtime = 873527 usecs, bandwidth 312 MB in 0.8735 sec = 375.12 MB/s ```
pablodelara commented 2026-09-08 04:02:49 -05:00 (Migrated from github.com)

@sunyuechi could you review this PR? Thanks!

@sunyuechi could you review this PR? Thanks!
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git switch 'master'
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